W83C553F Datasheet, PDF (61/159 Pages) Winbond – SYSTEM I/O CONTROLLER WITH PCI ARBITER

W83C553F
4.1.2
Function 0 Control Registers
Electrical Specifications
PCI Control Register (default = 20h)
Type:
Read/Write
Bit Description:
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
Reserved. This read only bit is set to "0".
Reserved.
IAE. Interrupt Acknowledge Enable. Setting this bit allows the W83C553F chip to respond to
the interrupt acknowledge command. This bit is active after reset.
Reserved. This read only bit is set to "0".
ESDP. Early Subtractive Decoding Point. Setting this bit will move the subtractive decoding
point one PCI clock earlier from "slow" to "medium" timing.
PWE. Post Write Enable. Setting this bit will allow PCI memory write cycles to the ISA bus to
be posted.
RETRYE. Retry Enable. When this bit is set to "1", PCI slave cycles are retried when the
internal bus is busy. When this bit is reset to "0" and the internal bus is busy, a PCI slave cycle
will be held in wait states until the bus becomes idle and the access completes. The default
state of this bit after a hardware reset is "0".
PCI NMI Enable. When set, PCI error status bits in the Status Register (except SSE) will
generate an NMI. Defaults to "0".
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