W83C553F Datasheet, PDF (17/159 Pages) Winbond – SYSTEM I/O CONTROLLER WITH PCI ARBITER

W83C553F
Pin Descriptions
Pin Name
PCICLK
A20M# /
PCIRST#
AD[31:0]
C/BE[3:0]#
PAR
Table 2-2. PCI Bus Signals
Pin #
Input/
Output Description
23
Input
Clock. Provides timing for all transactions on the PCI bus. Also
divides down to generate BCLK.
22
Output Address Bit 20 Mask or PCI Reset. This multi-function pin
functions as Address Bit 20 Mask when the W83C553F is in x86
mode, as determined by pin 8 strapping after power-up. It functions
as PCI Reset when the W83C553F is in PowerPC mode. It is driven
for one millisecond duration after one of the following conditions:
- PWRGD active edge
- Hot Reset is set (port 92, bit 0)
- Reset Drive is set (Clock Divisor Register bit 3)
PCI Reset is equivalent to ISA Reset logically inverted.
29-31,33-37,41- Input/
44, 46,47, 49, Output
50, 62-67,
69,71,73 -
79,81
39, 51, 61,
72
Input/
Output
Address or Data. These bits are multiplexed on the same PCI pins.
A valid 32-bit address is available during the address phase with
FRAME# asserted. All subsequent cycles are the data phases.
Bus Command and Byte Enables. These bits are multiplexed on the
same PCI pins. During the address phase of a transaction,
C/BE[3:0]# define the bus command. During the data phase,
C/BE[3:0]# are used for byte enables.
60
Input/ Parity. Even parity across AD[31:0] and C/BE[3:0]#. PAR is valid
Output one clock after the address phase. For data phases, PAR is valid one
clock after either IRDY# is asserted on the write transaction, or
TRDY# is asserted on a read transaction. PAR remains valid until
one clock after the completion of the current phase. PAR is driven
only for read data phases, and checked during write data phases.
WINBOND SYSTEMS LABORATORY
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