W83C553F Datasheet, PDF (76/159 Pages) Winbond – SYSTEM I/O CONTROLLER WITH PCI ARBITER

W83C553F
Electrical Specifications
DMA Break Event Enable Register (default = 00h)
Function:
This power management register may only be used while the W83C553F is in x86 mode.
Type:
Read/Write
Bit Description:
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
DRQ7. Enable DRQ7 as Break Event. When this bit is "1," DRQ7 detection is enabled. Upon
activation, the PMU will de-assert PMACT#.
DRQ6. Enable DRQ6 as Break Event. When this bit is "1," DRQ6 detection is enabled. Upon
activation, the PMU will de-assert PMACT#.
DRQ5. Enable DRQ5 as Break Event. When this bit is "1," DRQ5 detection is enabled. Upon
activation, the PMU will de-assert PMACT#.
DRQ4. Enable DRQ4 as Break Event. When this bit is "1," DRQ4 detection is enabled. Upon
activation, the PMU will de-assert PMACT#.
DRQ3. Enable DRQ3 as Break Event. When this bit is "1," DRQ3 detection is enabled. Upon
activation, the PMU will de-assert PMACT#.
DRQ2. Enable DRQ2 as Break Event. When this bit is "1," DRQ2 detection is enabled. Upon
activation, the PMU will de-assert PMACT#.
DRQ1. Enable DRQ1 as Break Event. When this bit is "1," DRQ1 detection is enabled. Upon
activation, the PMU will de-assert PMACT#.
DRQ0. Enable DRQ0 as Break Event. When this bit is "1," DRQ0 detection is enabled. Upon
activation, the PMU will de-assert PMACT#.
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