W83C553F Datasheet, PDF(35/159 Page) Winbond – SYSTEM I/O CONTROLLER WITH PCI ARBITER

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W83C553F Datasheet, PDF (35/159 Pages) Winbond – SYSTEM I/O CONTROLLER WITH PCI ARBITER

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W83C553F

Electrical Specifications

The next rising clock edge identifies the beginning of the data phase. Address parity is valid and will be checked or ignored

depending on the state of the SE bit of the Device Control Register. The data phase can last one or more clock cycles. Data

will be transferred on the rising clock edge when both IRDY# and TRDY# are asserted. Data parity will be generated (slave

I/O read or bus master memory write cycle) or checked (slave I/O write or bus master memory read cycle) on the next

rising clock edge. The W83C553F will report data parity errors on slave I/O write cycles it claims (by the assertion of

DEVSEL#) and bus master memory write cycles via the PERR# signal when enabled.

Normally for I/O cycles FRAME# will be de-asserted when IRDY# is asserted to signify that this is the last data transfer of

the data phase. STOP# will also be asserted with TRDY# to prevent I/O bursting. Multiple data phases (data bursting) are

supported when operating as a bus master.

Table 3-2 PCI Bus Cycles

C/BE[3:0]# PCI Bus Cycle

Slave Mode

Master Mode

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Interrupt Acknowledge

Special Cycle

I/O Read

I/O Write

Reserved

Memory Read

Memory Write

Reserved

Configuration Read

Configuration Write

Memory Read Multiple

Dual Address Cycle

Memory Read Line

Memory Write and Invalidate

Supported

Ignored

Supported

Ignored

Supported

Supported (aliased to Memory Read)

Ignored

Supported (aliased to Memory Read)

Supported (aliased to Memory Write)

Not Generated

Supported

Not Generated

Supported

Not Generated

Supported

WINBOND SYSTEMS LABORATORY

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