W83C553F Datasheet, PDF (136/159 Pages) Winbond – SYSTEM I/O CONTROLLER WITH PCI ARBITER

W83C553F
Electrical Specifications
4.4.3
Primary/Secondary PRD Table
(Base Address Register 4 value + offset: 07h-04h, 0Fh-0Ch)
These registers contain the starting address of the first Physical Region Descriptor Table in memory which applies to cases
where the W83C553F is functioning as a PCI bus master with one or more multi-word DMA mode disk drives. Bits 31
through 2 define a double word aligned address in memory. Bits 1 and 0 are reserved and will be ignored on writes and read
as 00b. The information in the descriptor table controls where the data is transferred to/from in system memory, how much
data is transferred and when the transfer is complete.
The descriptor table is composed of one or more Physical Region Descriptors. Each entry is two double words (8 bytes) and
is defined below.
Table 4-6. Physical Region Descriptor
Data Bits
Dword
31
16 15
0
0
Memory Region Physical Base Address (31:2)
00
1
EOT
Reserved
Byte Count
The Memory Region Physical Base Address specifies a word aligned address in memory that the bus master will transfer data
to/from.
The byte count specifies the number of bytes of data to transfer to this region of memory. The byte count is required to be
even (D0=0b). The maximum number of bytes defined in one descriptor entry is 64K which is selected by a value of 00h.
The number of bytes specified must not cause the memory region specified to cross a 64K boundary.
Bit 31 of double word 1 is the End Of Table flag. Bus master operation terminates upon completion of the descriptor entry
that has EOT set.
The Physical Region Descriptor Table cannot cross a 64K memory boundary.
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