W83C553F Datasheet, PDF (41/159 Pages) Winbond – SYSTEM I/O CONTROLLER WITH PCI ARBITER

W83C553F
Electrical Specifications
3.10 PCI Memory Read
The Memory Read command (C/BE[3:0]# = 6h during the address phase) is only used when operating as a bus master. It
will be used when transferring data to memory and the number of data phases is one half or less of the value programmed to
the Cache Line Size Register, or when reading less than 2 Dwords from memory. If the device needs to read more than 2
Dwords from memory, the Memory Read Line command is used. During the Memory Read cycle, the W83C553F issues a
PCI REQ# for the bus and, when PCI GNT# is asserted, reads one Dword from system memory. The bus is then released.
The data phase in Figure 3-6 takes two clock cycles, as determined by TRDY#. The W83C553F activates all byte enables,
even if some byte lanes do not contain valid data. It internally discards unnecessary bytes.
In slave mode, PCI-to-ISA memory reads are supported.
Figure 3-6. Master Memory Read Timing
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