W83C553F Datasheet, PDF (37/159 Pages) Winbond – SYSTEM I/O CONTROLLER WITH PCI ARBITER

W83C553F
Electrical Specifications
3.6 PCI I/O Read Cycle
Bursting is not supported by the W83C553F for I/O cycles, so a target disconnect will be executed after the first data transfer
on all I/O Read commands to prevent multiple I/O data phases.
Refer to Figure 3-2. The Slave I/O Read command (C/BE[3:0]# = 2h during address phase) is used by the processor to read
the W83C553F internal bus master registers, IDE device, and ISA registers or X-bus registers. It is a single, non-burst, 8, 16
or 32-bit transfer cycle, initiated by the CPU. It is a fixed duration, i.e. the W83C553F will assert TRDY# on the 4th bus
cycle of the transfer when accessing the internal bus master registers. It will have a variable duration when accessing an IDE
device or ISA register.
Figure 3-2. Slave I/O Read Timing
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