W83C553F Datasheet, PDF (101/159 Pages) Winbond – SYSTEM I/O CONTROLLER WITH PCI ARBITER

W83C553F
Electrical Specifications
Initialization Command Word 3 Register - PIC 1 (Master, default = 04h)
Function:
On the Interrupt Controller #1 (the master controller), this register indicates which IRQ line physically
connects the INT output of Interrupt Controller #2 (PIC 2) to Interrupt Controller #1 (PIC 1).
Type:
Write Only
Bit Description:
Bits [7:3]:
Bit 2:
Bits [1:0]:
SLAVE[7:3]. These bits must be programmed to "00000."
SLAVE2. Cascaded Interrupt Controller IRQ Connection. This bit must always be programmed
to "1." It indicates the slave controller (#2) is cascaded on IRQ2.
SLAVE[1:0]. These bits must be programmed to "00."
Initialization Command Word 3 Register - PIC 2 (Slave)
Function:
On the Interrupt Controller #2 (the slave controller), this register contains the slave identification code
broadcast by Interrupt Controller #1 from the trailing edge of the first INTA# pulse to the trailing edge of
the second INTA# pulse. It must be programmed to 02h for Interrupt Controller #2.
Type:
Write Only
Bit Description:
Bits [7:3]:
Bits [2:0]:
Reserved. These bits must be programmed to "00000."
SLVID[2:0]. Slave Identification Code. During the initialization sequence, bits 2 and 0 must be
programmed to "0" and bit 1 programmed to a "1."
WINBOND SYSTEMS LABORATORY
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