W83C553F Datasheet, PDF (24/159 Pages) Winbond – SYSTEM I/O CONTROLLER WITH PCI ARBITER

W83C553F
Pin Descriptions
Pin Name
BCLK
OSC
LA[23:17]
SA[16:0]
MASTER#
REFRESH#
MEMR#
MEMW#
Pin #
200
172
176,178,
180,182,
184,187,
189
144,145,
147-149,
151,152,
155,158,
160,162,
164,165,
167,169,
171,173
143
150
141
142
Table 2-5. ISA Bus Signals
Input/
Output Description
Output ISA Bus Clock.
Input
Oscillator. 14 MHz input for generating the internal timer clock.
Input/
Output
Latchable Address. The current bus owner drives LA[23:17] to
provide 16M of memory space.
Input/
Output
System Address. SA[16:0] provides the 17 least significant address
bits for memory accesses and SA[15:0] provides the entire 16
address bits for I/O accesses.
Input
ISA Master. Master control signal from the ISA bus.
Input/
Output
ISA DRAM Refresh Control. This pin is an open drain output and
allows other masters to initiate refresh requests.
Input/
Output
Memory Read. Acts as an output during PCI master and DMA
cycles and as an input during ISA master cycles.
Input/
Output
Memory Write. Acts as an output during PCI master and DMA
cycles and as an input during ISA master cycles.
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