W83C553F Datasheet, PDF (48/159 Pages) Winbond – SYSTEM I/O CONTROLLER WITH PCI ARBITER

W83C553F
Electrical Specifications
3.14.5
PCI Master Abort Timing
A Master Abort sequence is initiated by the W83C553F to abort its cycle if DEVSEL# is not asserted within four clocks after
FRAME# is asserted. This sequence is treated as a fatal error. Any IDE activity will be terminated immediately. An NMI
will be generated if programmed in register 40h, bit 0 (page 58.) The DMA Status Register's Abort and Error bits will be set.
The PCI Configuration Registers will not be cleared. The PCI Configuration Space Status Register's MA bit will also be set,
to indicate the W83C553F has terminated its transaction using a Master Abort cycle.
Figure 3-13. Master Abort Timing
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