W83C553F Datasheet, PDF (45/159 Pages) Winbond – SYSTEM I/O CONTROLLER WITH PCI ARBITER

W83C553F
Electrical Specifications
3.14.2
PCI Disconnect Without Data Transfer Timing
The Disconnect Without Data Transfer command cycle of Figure 3-10 shows a target disconnect when no data is transferred.
STOP# is asserted without TRDY# being asserted at the same time. The W83C553F terminates the current transfer with de-
assertion of FRAME#, and the de-assertion of IRDY#, at which point it releases the bus. The W83C553F will re-request the
bus after two clock cycles if more data is to be transferred. The starting address of the new transfer will be the address of the
next untransferred data (i.e. the address that the data would have been transferred to had the disconnect not occurred).
Figure 3-10. Disconnect Without Data Transfer Timing
WINBOND SYSTEMS LABORATORY
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