W83C553F Datasheet, PDF (133/159 Pages) Winbond – SYSTEM I/O CONTROLLER WITH PCI ARBITER

W83C553F
Electrical Specifications
4.4 Bus Master IDE (Function 1) I/O Registers
The Bus Master IDE Register set is defined by the PCI SIG. It is composed of 16 8-bit registers and is located at the I/O
address specified by Base Address Register 4. The registers can be accessed 8, 16, 24, or 32 bits at a time.
This register set is supplied to offer a higher performance lower overhead IDE disk protocol. With this protocol, the host
(PCI) transfers will be bus master cycles and the IDE device transfers will be DMA. The normal PIO protocol uses I/O
transfers on both the host and IDE interfaces. Primary and Secondary refer to the primary and secondary IDE ports. Both
register sets are identical.
Table 4-5. Bus Master IDE I/O Register Organization
Register Bits
Offset from
Base Address
31
24 23
16 15
87
0
03h - 00h
Reserved
Primary Status
Register
Reserved
Primary Command
Register
07h - 04h
Primary PRD Table Address
0Bh - 08h
Reserved
Secondary Status
Register
Reserved
Secondary Command
Register
0Fh - 0Ch
Secondary PRD Table Address
Note: The registers shown in Table 4-5 cannot be accessed until after Base Address Register 4 is written (with any non zero
value).
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