W83C553F Datasheet, PDF (74/159 Pages) Winbond – SYSTEM I/O CONTROLLER WITH PCI ARBITER

W83C553F
Electrical Specifications
IRQ Break Event Enable 1 Register (default = 00h)
Function:
This power management register may only be used while the W83C553F is in x86 mode.
Type:
Read/Write
Bit Description:
Bit 7:
IRQ15. Enable IRQ15 as Break Event. When this bit is "1," IRQ15 as Break Event detection is
enabled. Upon detection, the PMU will de-assert PMACT#.
Bit 6:
IRQ14. Enable IRQ14 as Break Event. When this bit is "1," IRQ14 as Break Event detection is
enabled. Upon detection, the PMU will de-assert PMACT#.
Bit 5:
IRQ13. Enable IRQ13 as Break Event. When this bit is "1," IRQ13 as Break Event detection is
enabled. Upon detection, the PMU will de-assert PMACT#.
Bit 4:
IRQ12. Enable IRQ12 as Break Event. When this bit is "1," IRQ12 as Break Event detection is
enabled. Upon detection, the PMU will de-assert PMACT#.
Bit 3:
IRQ11. Enable IRQ11 as Break Event. When this bit is "1," IRQ11 as Break Event detection is
enabled. Upon detection, the PMU will de-assert PMACT#.
Bit 2:
IRQ10. Enable IRQ10 as Break Event. When this bit is "1," IRQ10 as Break Event detection is
enabled. Upon detection, the PMU will de-assert PMACT#.
Bit 1:
IRQ9. Enable IRQ9 as Break Event. When this bit is "1," IRQ9 as Break Event detection is
enabled. Upon detection, the PMU will de-assert PMACT#.
Bit 0:
IRQ8. Enable IRQ8 as Break Event. When this bit is "1," IRQ8 as Break Event detection is
enabled. Upon detection, the PMU will de-assert PMACT#.
WINBOND SYSTEMS LABORATORY
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