W83C553F Datasheet, PDF (131/159 Pages) Winbond – SYSTEM I/O CONTROLLER WITH PCI ARBITER

W83C553F
Electrical Specifications
Type: Read/Write
Bit Description:
Bits [31:24]:
Bits [23:16]:
Bits [15:13]:
Bits [12:8]:
Bit 7:
Bit 6:
Bit 5:
Bits [4:0]:
Reserved. These bits are hardwired to a 0b.
User Defined. These bits are read/write and do not affect the operation of the W83C553F.
They can be used by the driver as a temporary storage. These bits will be 0b after reset.
Reserved. These bits are hardwired to a 0b.
CMD ON TIME. The value programmed to these bits controls the IDE_IOR# and IDE_IOW#
"ON" (low) time in clock cycles for this device. The actual number of clocks is the value
programmed plus one clock. The default value is 9h or 10 clocks. This value affects both PIO
and DMA timing.
PWEN. Posted write enable must be set to execute posted writes for this device. When this bit
is a 1b, posted writes are enabled. When this bit is a 0b, the default state, posted writes are
disabled.
RDYEN. When set, the IDE_IOCHRDY signal from the IDE interface is enabled and can insert
wait states when this device is accessed. When 0, the IDE_IOCHRDY signal will have no effect
on accesses to this device. This bit will be 0b after a reset.
RAEN. Read-ahead enable must be enabled to execute read-ahead for this device. When this
bit is a 1b, read-ahead is enabled. When this bit is a 0b, the default state, read-ahead is
disabled.
CMD OFF TIME. The value programmed to these bits controls the IDE_IOR# and IDE_IOW#
"OFF" (high) time in clock cycles for this device. The actual number of clocks is the value
programmed plus one clock. The default value is 9h or 10 clocks. This value affects both PIO
and DMA timing.
WINBOND SYSTEMS LABORATORY
128