W83C553F Datasheet, PDF (29/159 Pages) Winbond – SYSTEM I/O CONTROLLER WITH PCI ARBITER

W83C553F
Pin Descriptions
Pin Name Pin #
INT
10
NMI
11
INIT
3
SPKR
134
PWRGD
2
FERR#/IRQ13 12
IGNNE# / 4
HRESET#
Table 2-7. CPU Interface and Miscellaneous Signals
Input/
Output Description
Output Interrupt. Interrupt signal from the W83C553F interrupt controller to the
CPU.
Output Non-Maskable Interrupt.
Output
It functions as Initialize CPU/Software Reset (INIT) when the W83C553F
is in x86 mode, as determined by pin 8 strapping after reset. INIT is
asserted for four PCI clocks following one of these events:
- Hot Reset bit set (port 92, bit 0)
- CPU Shutdown Cycle
- keyboard Reset Emulation bit is set (bit 1, Index 4E)
Output Speaker Data. This output drives an externally buffered speaker.
Input
Power good signal from the power supply. This signal is used to generate
other reset signals to reset the system.
Input
This multi-function pin's default function is Interrupt Request 13 (IRQ13).
The Numerical Co-processor Error (FERR#) function may be enabled by a
bit in the Function 0 PCI Configuration Space AT System Control Register
(Index 4Eh, bit 4).
Output
This multi-function pin functions as Ignore Numeric Error (IGNNE#)
when the W83C553F is in x86 mode as determined by pin 8 strapping after
reset. It functions as HRESET# when the W83C553F is in PowerPC
mode. For connection to the PowerPC, HRESET# is asserted for a
duration of one millisecond after one of the following events:
- PWRGD active edge
- Hot Reset bit set (port 92, bit 0)
- CPU Shutdown Cycle
- Keyboard Reset Emulation bit is set (bit 1, Index 4E)
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