W83C553F Datasheet, PDF (147/159 Pages) Winbond – SYSTEM I/O CONTROLLER WITH PCI ARBITER

W83C553F
Timing Diagrams
Table 6-6 (continued). PIO ATA Data Transfer Timing
Parameter
t2 IDEIOR[A:B]# / IDEIOW[A:B]# Mode 0
16-bit
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
t2 Pulse Width 8-bit
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
t2i IDEIOR[A:B]# / IDEIOW[A:B]# Mode 0
recovery time
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
t3 IDEIOW[A:B]#
data setup
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
t4 IDEIOW[A:B]# data hold
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Values
Min
Max
Notes
165ns
125ns
100ns
80ns
70ns
t0 is the minimum total cycle time, t2 is the
minimum command active time, and t2i is
the minimum command recovery time or
command inactive time. The actual cycle
time equals the sum of the actual command
290ns
290ns
290ns
80ns
70ns
active time and the actual command inactive
time. The three timing requirements of t0,
t2, t2i shall be met. The minimum total
cycle time requirement, t0, is greater than
the sum of t2 and t2i. This means host
implementation
can lengthen either or both t2 and t2i. to
-
ensure that t0 is equal to the value reported
-
in the devices identify drive data. A device
-
implementation shall support any legal host
70ns
implementation.
25ns
60ns
45ns
30ns
30ns
20ns
30ns
20ns
15ns
10ns
10ns
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