W83C553F Datasheet, PDF (148/159 Pages) Winbond – SYSTEM I/O CONTROLLER WITH PCI ARBITER

W83C553F
Timing Diagrams
Table 6-6 (continued). PIO ATA Data Transfer Timing
Parameter
t5 IDEIOR[A:B]# data setup
t6 IDEIOR[A:B]# data hold
t6z IDEIOR[A:B]# data
tri-state
t9 IDEIOR[A:B]# /
IDEIOW[A:B]#
to address valid hold
tR Read data valid to
IDECHRDY active
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Values
Min
Max
50ns
35ns
20ns
20ns
20ns
Notes
5ns
5ns
5ns
5ns
5ns
- This parameter specifies the time from the
- negation edge of IDEIOR[A:B]# to the time
- that the data bus is no longer driven by the
30ns device (tri-state).
30ns
20ns
15ns
10ns
10ns
5ns
-
If IDE_IOCHRDY is initially asserted after
-
tA.
-
0ns
0ns
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