W83C553F Datasheet, PDF (43/159 Pages) Winbond – SYSTEM I/O CONTROLLER WITH PCI ARBITER

W83C553F
Electrical Specifications
3.12 PCI Memory Read Line
The Memory Read Line command (C/BE[3:0]# = Eh during the address phase) is only used when operating as a bus master.
It will be used when transferring data to memory and the number of data phases is at least two double words and is greater
than one half of the value programmed to the Cache Line Size Register.
In Figure 3-8, the W83C553F issues a request for the bus and, when access is granted, reads eight Dwords from system
memory before releasing the bus. All data phases in this figure take one clock cycle, as determined by TRDY#.
Figure 3-8. Master Memory Read Line Timing
3.13 PCI Memory Write and Invalidate
The Memory Write and Invalidate command (C/BE[3:0]# = Fh during the address phase) is only used when operating as a
bus master and enabled as indicated by the state of the MWIEN bit of the Device Control Register. It will be used when
transferring data from memory and entire cache line(s) will be written (as programmed to the Cache Line Size Register).
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