W83C553F Datasheet, PDF (118/159 Pages) Winbond – SYSTEM I/O CONTROLLER WITH PCI ARBITER

W83C553F
Electrical Specifications
Device Status Register (default = 0280h)
Function:
The Device Status Register is used to record status information for PCI bus related events. Reads to this
register behave normally. Writes report slightly different, in that bits can be reset, but not set. A bit is reset
whenever the register is written, and the data in the corresponding bit is a 1b. In the cases of PE, SE, MA,
RTA, TA, or MPE been set, the software should write a “1” in the corresponding bit position to clear it,
after recovering from the error.
Type: Read/Write
Bit Description:
Bit 15:
Bit 14:
Bit 13:
Bit 12:
Bit 11:
PE. This bit is set anytime a parity error is detected during a slave data write to the W83C553F,
for any command phase parity error, or when operating as a bus master for any memory read
parity error. The function of this bit is not affected by the Device Control Register parity bit.
SE. This bit is set anytime the W83C553F asserts the SERR# output low.
MA. This bit will be set when operating as a bus master and a (memory) cycle is terminated
with master abort.
RTA. This bit will be set when operating as a bus master and a (memory) cycle is terminated
with target abort.
TA. The target abort bit will be set anytime the W83C553F terminates a slave cycle with a
target abort cycle.
WINBOND SYSTEMS LABORATORY
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