W83C553F Datasheet, PDF (25/159 Pages) Winbond – SYSTEM I/O CONTROLLER WITH PCI ARBITER

W83C553F
Pin Descriptions
Pin Name
IOR#
IOW#
SMEMR#
SMEMW#
ZWS#
SBHE#
M16#
IO16#
IOCHK#
Pin #
140
139
138
137
132
174
175
177
122
Table 2-5 (Continued). ISA Bus Signals
Input/
Output Description
Input/
Output
I/O Read. Act as an output during PCI master and DMA cycles and
as an input during ISA master cycles.
Input/
Output
I/O Write. Act as an output during PCI master and DMA cycles and
as input during ISA master cycles.
Output
Memory Read To Address Below 1M. An external pull-up resistor
is required.
Output
Memory Write To Address Below 1M. An external pull-up resistor
is required.
Input
Zero Wait State. This signal is used by ISA slaves to terminate a
transfer cycle before the default ready counter expires.
Input/
Output
System Byte High Enable. SBHE# is asserted to indicate that data
is being transferred on SD[15:8].
Input/
Output
Memory Cycle 16-Bit Select. This signal is used by memory slaves
to indicate 16-bit transfer capability.
Input
I/O Cycle 16-Bit Select. This signal is used by I/O slaves to
indicate 16-bit transfer capability.
Input
I/O Channel Check. This assertion of this signal indicates an error
has occurred.
WINBOND SYSTEMS LABORATORY
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