W83C553F Datasheet, PDF (152/159 Pages) Winbond – SYSTEM I/O CONTROLLER WITH PCI ARBITER

W83C553F
Timing Diagrams
Table 6-8 (continued). Multiword DMA ATA Data Transfer Timing
Parameter
tE IDEIOR[A:B]#
data access
Mode 0
Mode 1
Mode 2
Mode 3
Values
Min
Max
150ns
60ns
-
Notes
tF IDEIOR[A:B]#
read data hold
Mode 0
5ns
Mode 1
5ns
Mode 2
5ns
Mode 3
* The meaning of this parameter in ATA is
not clear. The parameter is not applicable to
* this specification.
tZ IDEDAK[A:B]#
to tri-state
Mode 0
20ns
Mode 1
25ns
Mode 2
25ns
Mode 3
This parameter specifies the time from the
negation edge of DIOR# to the time that the
data bus is no longer driven by the device
(tristate).
tG IDEIOR[A:B]# /
IDEIOW[A:B]#
data setup
Mode 0
Mode 1
Mode 2
Mode 3
100ns
30ns
20ns
tH IDEIOR[A:B]# /
IDEIOW[A:B]#
write data hold
Mode 0
20ns
Mode 1
15ns
Mode 2
10ns
Mode 3
WINBOND SYSTEMS LABORATORY
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