W83C553F Datasheet, PDF (119/159 Pages) Winbond – SYSTEM I/O CONTROLLER WITH PCI ARBITER

W83C553F
Electrical Specifications
Bit [10:9]
Bit 8:
Bit 7:
Bit [6:0]:
DSTMG. These bits encode the timing of DEVSEL#. They are hardwired to 01b indicating the
support of medium DEVSEL# timing. This allows for support of fast back-to-back PCI bus
cycles. This will maximize the PCI bus bandwidth for PIO data transfer cycles.
MPE. This bit will be set when operating as a bus master and either the PERR# output is
driven low by the W83C553F or the target asserts PERR# and bit 6 of the Device Control
Register is set.
FBB. This bit will always be set. The W83C553F fully supports fast back to back transactions
to different targets.
These bits are reserved and are hardwired to logic 0b.
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