W83C553F Datasheet, PDF (153/159 Pages) Winbond – SYSTEM I/O CONTROLLER WITH PCI ARBITER

W83C553F
Timing Diagrams
Table 6-8 (continued). Multiword DMA ATA Data Transfer Timing
Parameter
tI IDEDAK[A:B]# to
IDEIOR[A:B]# /
IDEIOW[A:B]#
setup
tJ IDEIOR[A:B]# /
IDEIOW[A:B]# to
IDEDAK[A:B]#
hold
tKr IDEIOR[A:B]# negated
pulse width
tKw IDEIOW[A:B]# negated
pulse width
tLr IDEIOR[A:B]# to
IDEDRQ[A:B] delay
tLw IDEIOW[A:B]# to
IDEDRQ[A:B] delay
Mode 0
Mode 1
Mode 2
Mode 3
Mode 0
Mode 1
Mode 2
Mode 3
Mode 0
Mode 1
Mode 2
Mode 3
Mode 0
Mode 1
Mode 2
Mode 3
Mode 0
Mode 1
Mode 2
Mode 3
Mode 0
Mode 1
Mode 2
Mode 3
Values
Min
Max
0ns
0ns
0ns
Notes
20ns
5ns
5ns
50ns
50ns
25ns
215ns
50ns
25ns
The delay from DIOR# or DIOW# until the
state of IORDY is first sampled. If IORDY
is inactive, then the host shall wait until
IORDY is active before the PIO cycle can be
completed. If the device is not driving
IORDY negated at the time tA after the
activation of DIOR# or DIOW#, then t5
shall be met and tRD is not applicable. If
the device is driving IORDY negated at the
time tA after the activation of DIOR# or
DIOW#, then tRD shall be met and t5 is not
applicable.
120ns
40ns
35ns
40ns
40ns
35ns
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