LM3S5956-IQR80-C1 Datasheet, PDF (993/1144 Pages) Texas Instruments – Stellaris® LM3S5956 Microcontroller

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Stellaris^® LM3S5956 Microcontroller
Bit/Field
3
2
1
0
Name
INTCMPAD
INTCMPAU
INTCNTLOAD
INTCNTZERO
Type
R/W1C
R/W1C
R/W1C
R/W1C
Reset
0
0
0
0
Description
Comparator A Down Interrupt
Value Description
1 The INTCMPAD bits in the PWMnRIS and PWMnINTEN registers
are set, providing an interrupt to the interrupt controller.
0 No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1. Clearing this bit also clears the
INTCMPAD bit in the PWMnRIS register.
Comparator A Up Interrupt
Value Description
1 The INTCMPAU bits in the PWMnRIS and PWMnINTEN registers
are set, providing an interrupt to the interrupt controller.
0 No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1. Clearing this bit also clears the
INTCMPAU bit in the PWMnRIS register.
Counter=Load Interrupt
Value Description
1 The INTCNTLOAD bits in the PWMnRIS and PWMnINTEN
registers are set, providing an interrupt to the interrupt controller.
0 No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1. Clearing this bit also clears the
INTCNTLOAD bit in the PWMnRIS register.
Counter=0 Interrupt
Value Description
1 The INTCNTZERO bits in the PWMnRIS and PWMnINTEN
registers are set, providing an interrupt to the interrupt controller.
0 No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1. Clearing this bit also clears the
INTCNTZERO bit in the PWMnRIS register.
October 06, 2012
993
Texas Instruments-Production Data