LM3S5956-IQR80-C1 Datasheet, PDF (91/1144 Pages) Texas Instruments – Stellaris® LM3S5956 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S5956 Microcontroller
2.4.3
2.4.4
Behavior of Memory Accesses
Table 2-5 on page 91 shows the behavior of accesses to each region in the memory map. See
“Memory Regions, Types and Attributes” on page 90 for more information on memory types and
the XN attribute. Stellaris devices may have reserved memory areas within the address ranges
shown below (refer to Table 2-4 on page 88 for more information).
Table 2-5. Memory Access Behavior
Address Range
Memory Region
0x0000.0000 - 0x1FFF.FFFF Code
Memory Type Execute
Never
(XN)
Normal
-
0x2000.0000 - 0x3FFF.FFFF SRAM
Normal
-
0x4000.0000 - 0x5FFF.FFFF Peripheral
Device
XN
0x6000.0000 - 0x9FFF.FFFF External RAM
Normal
-
0xA000.0000 - 0xDFFF.FFFF External device Device
XN
0xE000.0000- 0xE00F.FFFF Private peripheral Strongly
XN
bus
Ordered
0xE010.0000- 0xFFFF.FFFF Reserved
-
-
Description
This executable region is for program code.
Data can also be stored here.
This executable region is for data. Code
can also be stored here. This region
includes bit band and bit band alias areas
(see Table 2-6 on page 93).
This region includes bit band and bit band
alias areas (see Table 2-7 on page 93).
This executable region is for data.
This region is for external device memory.
This region includes the NVIC, system
timer, and system control block.
-
The Code, SRAM, and external RAM regions can hold programs. However, it is recommended that
programs always use the Code region because the Cortex-M3 has separate buses that can perform
instruction fetches and data accesses simultaneously.
The MPU can override the default memory access behavior described in this section. For more
information, see “Memory Protection Unit (MPU)” on page 114.
The Cortex-M3 prefetches instructions ahead of execution and speculatively prefetches from branch
target addresses.
Software Ordering of Memory Accesses
The order of instructions in the program flow does not always guarantee the order of the
corresponding memory transactions for the following reasons:
■ The processor can reorder some memory accesses to improve efficiency, providing this does
not affect the behavior of the instruction sequence.
■ The processor has multiple bus interfaces.
■ Memory or devices in the memory map have different wait states.
■ Some memory accesses are buffered or speculative.
“Memory System Ordering of Memory Accesses” on page 90 describes the cases where the memory
system guarantees the order of memory accesses. Otherwise, if the order of memory accesses is
critical, software must include memory barrier instructions to force that ordering. The Cortex-M3
has the following memory barrier instructions:
October 06, 2012
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