LM3S5956-IQR80-C1 Datasheet, PDF (5/1144 Pages) Texas Instruments – Stellaris® LM3S5956 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S5956 Microcontroller
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Hibernation Module .............................................................................................. 290
6.1 Block Diagram ............................................................................................................ 291
6.2 Signal Description ....................................................................................................... 291
6.3 Functional Description ................................................................................................. 292
6.3.1 Register Access Timing ............................................................................................... 292
6.3.2 Hibernation Clock Source ............................................................................................ 292
6.3.3 System Implementation ............................................................................................... 294
6.3.4 Battery Management ................................................................................................... 294
6.3.5 Real-Time Clock .......................................................................................................... 295
6.3.6 Battery-Backed Memory .............................................................................................. 295
6.3.7 Power Control Using HIB ............................................................................................. 295
6.3.8 Power Control Using VDD3ON Mode ........................................................................... 296
6.3.9 Initiating Hibernate ...................................................................................................... 296
6.3.10 Waking from Hibernate ................................................................................................ 296
6.3.11 Interrupts and Status ................................................................................................... 296
6.4 Initialization and Configuration ..................................................................................... 297
6.4.1 Initialization ................................................................................................................. 297
6.4.2 RTC Match Functionality (No Hibernation) .................................................................... 298
6.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 298
6.4.4 External Wake-Up from Hibernation .............................................................................. 298
6.4.5 RTC or External Wake-Up from Hibernation .................................................................. 298
6.5 Register Map .............................................................................................................. 299
6.6 Register Descriptions .................................................................................................. 299
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7.1
7.2
7.2.1
7.2.2
7.2.3
7.3
7.4
7.5
Internal Memory ................................................................................................... 316
Block Diagram ............................................................................................................ 316
Functional Description ................................................................................................. 316
SRAM ........................................................................................................................ 317
ROM .......................................................................................................................... 317
Flash Memory ............................................................................................................. 319
Register Map .............................................................................................................. 324
Flash Memory Register Descriptions (Flash Control Offset) ............................................ 325
Memory Register Descriptions (System Control Offset) .................................................. 337
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Micro Direct Memory Access (μDMA) ................................................................ 353
8.1 Block Diagram ............................................................................................................ 354
8.2 Functional Description ................................................................................................. 354
8.2.1 Channel Assignments .................................................................................................. 355
8.2.2 Priority ........................................................................................................................ 356
8.2.3 Arbitration Size ............................................................................................................ 356
8.2.4 Request Types ............................................................................................................ 356
8.2.5 Channel Configuration ................................................................................................. 357
8.2.6 Transfer Modes ........................................................................................................... 359
8.2.7 Transfer Size and Increment ........................................................................................ 367
8.2.8 Peripheral Interface ..................................................................................................... 367
8.2.9 Software Request ........................................................................................................ 367
8.2.10 Interrupts and Errors .................................................................................................... 368
8.3 Initialization and Configuration ..................................................................................... 368
8.3.1 Module Initialization ..................................................................................................... 368
8.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 368
October 06, 2012
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