LM3S5956-IQR80-C1 Datasheet, PDF (14/1144 Pages) Texas Instruments – Stellaris® LM3S5956 Microcontroller

Table of Contents
NRND: Not recommended for new designs.
List of Tables
Table 1.
Table 2.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 2-13.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-8.
Table 3-9.
Table 4-1.
Table 4-2.
Table 4-3.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 5-8.
Table 6-1.
Table 6-2.
Table 6-3.
Table 7-1.
Table 7-2.
Table 7-3.
Table 8-1.
Table 8-2.
Table 8-3.
Table 8-4.
Table 8-5.
Revision History .................................................................................................. 37
Documentation Conventions ................................................................................ 47
Summary of Processor Mode, Privilege Level, and Stack Use ................................ 74
Processor Register Map ....................................................................................... 75
PSR Register Combinations ................................................................................. 80
Memory Map ....................................................................................................... 88
Memory Access Behavior ..................................................................................... 91
SRAM Memory Bit-Banding Regions .................................................................... 93
Peripheral Memory Bit-Banding Regions ............................................................... 93
Exception Types .................................................................................................. 99
Interrupts ............................................................................................................ 99
Exception Return Behavior ................................................................................. 104
Faults ............................................................................................................... 105
Fault Status and Fault Address Registers ............................................................ 106
Cortex-M3 Instruction Summary ......................................................................... 108
Core Peripheral Register Regions ....................................................................... 111
Memory Attributes Summary .............................................................................. 114
TEX, S, C, and B Bit Field Encoding ................................................................... 117
Cache Policy for Memory Attribute Encoding ....................................................... 118
AP Bit Field Encoding ........................................................................................ 118
Memory Region Attributes for Stellaris Microcontrollers ........................................ 118
Peripherals Register Map ................................................................................... 119
Interrupt Priority Levels ...................................................................................... 146
Example SIZE Field Values ................................................................................ 174
JTAG_SWD_SWO Signals (64LQFP) ................................................................. 178
JTAG Port Pins State after Power-On Reset or RST assertion .............................. 179
JTAG Instruction Register Commands ................................................................. 185
System Control & Clocks Signals (64LQFP) ........................................................ 189
Reset Sources ................................................................................................... 190
Clock Source Options ........................................................................................ 197
Possible System Clock Frequencies Using the SYSDIV Field ............................... 200
Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 200
Examples of Possible System Clock Frequencies with DIV400=1 ......................... 201
System Control Register Map ............................................................................. 206
RCC2 Fields that Override RCC Fields ............................................................... 227
Hibernate Signals (64LQFP) ............................................................................... 291
Hibernation Module Clock Operation ................................................................... 297
Hibernation Module Register Map ....................................................................... 299
Flash Memory Protection Policy Combinations .................................................... 320
User-Programmable Flash Memory Resident Registers ....................................... 324
Flash Register Map ............................................................................................ 324
μDMA Channel Assignments .............................................................................. 355
Request Type Support ....................................................................................... 357
Control Structure Memory Map ........................................................................... 358
Channel Control Structure .................................................................................. 358
μDMA Read Example: 8-Bit Peripheral ................................................................ 367
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October 06, 2012
Texas Instruments-Production Data