LM3S5956-IQR80-C1 Datasheet, PDF (192/1144 Pages) Texas Instruments – Stellaris® LM3S5956 Microcontroller

System Control
NRND: Not recommended for new designs.
Figure 5-1. Basic RST Configuration
VDD
Stellaris®
R_PU
RST
R_PU = 0 to 100 kΩ
The external reset pin (RST) resets the microcontroller including the core and all the on-chip
peripherals except the JTAG TAP controller (see “JTAG Interface” on page 177). The external reset
sequence is as follows:
1. The external reset pin (RST) is asserted for the duration specified by T_MIN and then de-asserted
(see “Reset” on page 1072).
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, and the first instruction designated by the program counter, and then begins
execution.
To improve noise immunity and/or to delay reset at power up, the RST input may be connected to
an RC network as shown in Figure 5-2 on page 192.
Figure 5-2. External Circuitry to Extend Power-On Reset
VDD
Stellaris®
R_PU
RST
C₁
R_PU = 1 kΩ to 100 kΩ
C₁ = 1 nF to 10 µF
If the application requires the use of an external reset switch, Figure 5-3 on page 193 shows the
proper circuitry to use.
192
October 06, 2012
Texas Instruments-Production Data