LM3S5956-IQR80-C1 Datasheet, PDF (11/1144 Pages) Texas Instruments – Stellaris® LM3S5956 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S5956 Microcontroller
List of Figures
Figure 1-1.
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Figure 2-7.
Figure 3-1.
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure 4-4.
Figure 4-5.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 6-1.
Figure 6-2.
Figure 6-3.
Figure 7-1.
Figure 8-1.
Figure 8-2.
Figure 8-3.
Figure 8-4.
Figure 8-5.
Figure 8-6.
Figure 9-1.
Figure 9-2.
Figure 9-3.
Figure 9-4.
Figure 10-1.
Figure 10-2.
Figure 10-3.
Figure 10-4.
Figure 10-5.
Figure 11-1.
Figure 12-1.
Figure 12-2.
Figure 12-3.
Figure 12-4.
Figure 12-5.
Figure 12-6.
Stellaris LM3S5956 Microcontroller High-Level Block Diagram ............................... 50
CPU Block Diagram ............................................................................................. 71
TPIU Block Diagram ............................................................................................ 72
Cortex-M3 Register Set ........................................................................................ 74
Bit-Band Mapping ................................................................................................ 94
Data Storage ....................................................................................................... 95
Vector Table ...................................................................................................... 101
Exception Stack Frame ...................................................................................... 103
SRD Use Example ............................................................................................. 117
JTAG Module Block Diagram .............................................................................. 178
Test Access Port State Machine ......................................................................... 181
IDCODE Register Format ................................................................................... 187
BYPASS Register Format ................................................................................... 187
Boundary Scan Register Format ......................................................................... 188
Basic RST Configuration .................................................................................... 192
External Circuitry to Extend Power-On Reset ....................................................... 192
Reset Circuit Controlled by Switch ...................................................................... 193
Power Architecture ............................................................................................ 196
Main Clock Tree ................................................................................................ 199
Hibernation Module Block Diagram ..................................................................... 291
Using a Crystal as the Hibernation Clock Source ................................................. 293
Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON
Mode ................................................................................................................ 294
Internal Memory Block Diagram .......................................................................... 316
μDMA Block Diagram ......................................................................................... 354
Example of Ping-Pong μDMA Transaction ........................................................... 360
Memory Scatter-Gather, Setup and Configuration ................................................ 362
Memory Scatter-Gather, μDMA Copy Sequence .................................................. 363
Peripheral Scatter-Gather, Setup and Configuration ............................................. 365
Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 366
Digital I/O Pads ................................................................................................. 414
Analog/Digital I/O Pads ...................................................................................... 415
GPIODATA Write Example ................................................................................. 416
GPIODATA Read Example ................................................................................. 416
GPTM Module Block Diagram ............................................................................ 463
Timer Daisy Chain ............................................................................................. 467
Input Edge-Count Mode Example ....................................................................... 469
16-Bit Input Edge-Time Mode Example ............................................................... 471
16-Bit PWM Mode Example ................................................................................ 472
WDT Module Block Diagram .............................................................................. 509
Implementation of Two ADC Blocks .................................................................... 534
ADC Module Block Diagram ............................................................................... 535
ADC Sample Phases ......................................................................................... 538
Doubling the ADC Sample Rate .......................................................................... 539
Skewed Sampling .............................................................................................. 539
Sample Averaging Example ............................................................................... 540
October 06, 2012
11
Texas Instruments-Production Data