LM3S5956-IQR80-C1 Datasheet, PDF (40/1144 Pages) Texas Instruments – Stellaris® LM3S5956 Microcontroller

Revision History
NRND: Not recommended for new designs.
Table 1. Revision History (continued)
Date
January 2011
Revision Description
9161 ■ Clarified Main Oscillator verification circuit sequence.
■ Added note that there must be a delay of 3 system clocks after the module clock is enabled before
any of that module's registers are accessed.
■ Corrected reset of Device Mode (DEVMOD) bitfield in USB General-Purpose Control and Status
(USBGPCS) register.
■ Clarified initialization and configuration procedure in "Analog Comparators" chapter.
■ In Electrical Characteristics chapter:
– Added specification for maximum input voltage on a non-power pin when the microcontroller is
unpowered (V_NON parameter in Maximum Ratings table).
– Replaced Preliminary Current Consumption Specifications with Nominal Power Consumption,
Maximum Current Specifications, and Typical Current Consumption vs. Frequency sections.
– Clarified Reset, and Power and Brown-out Characteristics and added a new specification for
powering down before powering back up.
– Added characteristics required when using an external regulator to provide power for V_DDC.
■ Additional minor data sheet clarifications and corrections.
December 2010
8832
■ Information on Advanced Encryption Standard (AES) cryptography tables and Cyclic Redundancy
Check (CRC) error detection functionality was inadvertently omitted from some datasheets. This
has been added.
■ In APINT register, changed bit name from SYSRESETREQ to SYSRESREQ.
■ Added DEBUG (Debug Priority) bit field to SYSPRI3 register.
■ Clarified Flash memory caution.
■ Restructured the General-Purpose Timer chapter to combine duplicated text.
■ Combined High and Low bit fields in GPTMTAILR, GPTMTAMATCHR, GPTMTAR, GPTMTAV,
GPTMTBILR, GPTMTAMATCHR, GPTMTBR and GPTMTBV registers for compatibility with future
releases.
■ Removed mention of false-start bit detection in the UART chapter. This feature is not supported.
■ Added SSI master clock restriction that SSIClk cannot be faster than 25 MHz.
■ Changed I²C master and slave register base addresses and offsets to be relative to I²C module
base, so register base and offsets were changed for all I²C slave registers.
■ In Electrical Characteristics chapter:
– Added single-ended clock source input voltage values to "Recommended DC Operating
Conditions" table.
– Deleted Oscillation mode value from "MOSC Oscillator Input Characteristics" table.
– Added T_{VDD2_3} supply voltage parameter to "Reset Characteristics" table.
– Added "Power-On Reset and Voltage Parameters" timing diagram.
– Added t_{VDDRISE_HIB} supply voltage parameter to "Hibernation Module AC Characteristics" table.
– Added "VDD Ramp when Waking from Hibernation" timing diagram.
40
October 06, 2012
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