LM3S5956-IQR80-C1 Datasheet, PDF (140/1144 Pages) Texas Instruments – Stellaris® LM3S5956 Microcontroller

Cortex-M3 Peripherals
NRND: Not recommended for new designs.
Bit/Field
0
Name
DISMCYC
Type
R/W
Reset
0
Description
Disable Interrupts of Multiple Cycle Instructions
Value Description
0 No effect.
1 Disables interruption of load multiple and store multiple
instructions. In this situation, the interrupt latency of the
processor is increased because any LDM or STM must complete
before the processor can stack the current state and enter the
interrupt handler.
140
October 06, 2012
Texas Instruments-Production Data