LM3S5956-IQR80-C1 Datasheet, PDF (284/1144 Pages) Texas Instruments – Stellaris® LM3S5956 Microcontroller

System Control
NRND: Not recommended for new designs.
Bit/Field
16
15:7
6
5:4
3
2:0
Name
ADC0
reserved
HIB
reserved
WDT0
reserved
Type
R/W
RO
R/W
RO
R/W
RO
Reset
0
0
0
0
0
0
Description
ADC0 Reset Control
When this bit is set, ADC module 0 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
HIB Reset Control
When this bit is set, the Hibernation module is reset. All internal data is
lost and the registers are returned to their reset states.This bit must be
manually cleared after being set.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
WDT0 Reset Control
When this bit is set, Watchdog Timer module 0 is reset. All internal data
is lost and the registers are returned to their reset states. This bit must
be manually cleared after being set.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
284
October 06, 2012
Texas Instruments-Production Data