LM3S5956-IQR80-C1 Datasheet, PDF (569/1144 Pages) Texas Instruments – Stellaris® LM3S5956 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S5956 Microcontroller
Bit/Field
3:0
Name
EM0
Type
R/W
Reset
0x0
Description
SS0 Trigger Select
This field selects the trigger source for Sample Sequencer 0
The valid configurations for this field are:
Value Event
0x0
Processor (default)
The trigger is initiated by setting the SSn bit in the ADCPSSI
register.
0x1
Analog Comparator 0
This trigger is configured by the Analog Comparator Control
0 (ACCTL0) register (page 945).
0x2
Analog Comparator 1
This trigger is configured by the Analog Comparator Control
1 (ACCTL1) register (page 945).
0x3
reserved
0x4
External (GPIO PB4)
This trigger is connected to the GPIO interrupt for PB4 (see
“ADC Trigger Source” on page 417).
0x5
Timer
In addition, the trigger must be enabled with the TnOTE bit
in the GPTMCTL register (page 483).
0x6
PWM0
The PWM generator 0 trigger can be configured with the
PWM0 Interrupt and Trigger Enable (PWM0INTEN) register
(page 987).
0x7
PWM1
The PWM generator 1 trigger can be configured with the
PWM1INTEN register (page 987).
0x8
PWM2
The PWM generator 2 trigger can be configured with the
PWM2INTEN register (page 987).
0x9
reserved
0xA-0xE reserved
0xF
Always (continuously sample)
October 06, 2012
569
Texas Instruments-Production Data