LM3S5956-IQR80-C1 Datasheet, PDF (296/1144 Pages) Texas Instruments – Stellaris® LM3S5956 Microcontroller

Hibernation Module
NRND: Not recommended for new designs.
6.3.8
6.3.9
6.3.10
6.3.11
external regulator is turned off and no longer powers the microcontroller and any parts of the system
that are powered by the regulator. The Hibernation module remains powered from the V_BAT supply
(which could be a battery or an auxiliary power source) until a Wake event. Power to the
microcontroller is restored by deasserting the HIB signal, which causes the external regulator to
turn power back on to the chip.
Power Control Using VDD3ON Mode
The Hibernation module may also be configured to cut power to all internal modules. While in this
state, all pins are configured as inputs. In the VDD3ON mode, the regulator should maintain 3.3 V
power to the microcontroller during Hibernate. This power control mode is enabled by setting the
VDD3ON bit in HIBCTL.
Initiating Hibernate
Hibernate mode is initiated when the HIBREQ bit of the HIBCTL register is set. If a wake-up condition
has not been configured using the PINWEN or RTCWEN bits in the HIBCTL register, the hibernation
request is ignored. If a Flash memory write operation is in progress when the HIBREQ bit is set, an
interlock feature holds off the transition into Hibernate mode until the write has completed.
Waking from Hibernate
The Hibernation module is configured to wake from the external WAKE pin by setting the PINWEN
bit of the HIBCTL register. It is configured to wake from RTC match by setting the RTCWEN bit. Note
that the WAKE pin uses the Hibernation module's internal power supply as the logic 1 reference.
Upon either external wake-up or RTC match, the Hibernation module delays coming out of hibernation
until V_DD is above the minimum specified voltage, see Table 24-2 on page 1068.
When the Hibernation module wakes, the microcontroller performs a normal power-on reset. Note
that this reset does not reset the Hibernation module, but does reset the rest of the microcontroller.
Software can detect that the power-on was due to a wake from hibernation by examining the raw
interrupt status register (see “Interrupts and Status” on page 296) and by looking for state data in
the battery-backed memory (see “Battery-Backed Memory” on page 295).
Interrupts and Status
The Hibernation module can generate interrupts when the following conditions occur:
■ Assertion of WAKE pin
■ RTC match
■ Low battery detected
All of the interrupts are ORed together before being sent to the interrupt controller, so the Hibernate
module can only generate a single interrupt request to the controller at any given time. The software
interrupt handler can service multiple interrupt events by reading the Hibernation Masked Interrupt
Status (HIBMIS) register. Software can also read the status of the Hibernation module at any time
by reading the HIBRIS register which shows all of the pending events. This register can be used
after waking from hibernation to see if the wake condition was caused by the WAKE signal or the
RTC match.
The events that can trigger an interrupt are configured by setting the appropriate bits in the
Hibernation Interrupt Mask (HIBIM) register. Pending interrupts can be cleared by writing the
corresponding bit in the Hibernation Interrupt Clear (HIBIC) register.
296
October 06, 2012
Texas Instruments-Production Data