LM3S5956-IQR80-C1 Datasheet, PDF (90/1144 Pages) Texas Instruments – Stellaris® LM3S5956 Microcontroller

The Cortex-M3 Processor
NRND: Not recommended for new designs.
Table 2-4. Memory Map (continued)
Start
End
0x400F.F000
0x4010.0000
0x4200.0000
0x4400.0000
Private Peripheral Bus
0xE000.0000
0xE000.1000
0xE000.2000
0xE000.3000
0xE000.E000
0xE000.F000
0xE004.0000
0xE004.1000
0x400F.FFFF
0x41FF.FFFF
0x43FF.FFFF
0xDFFF.FFFF
0xE000.0FFF
0xE000.1FFF
0xE000.2FFF
0xE000.DFFF
0xE000.EFFF
0xE003.FFFF
0xE004.0FFF
0xFFFF.FFFF
Description
µDMA
Reserved
Bit-banded alias of 0x4000.0000 through 0x400F.FFFF
Reserved
For details,
see page ...
374
-
-
-
Instrumentation Trace Macrocell (ITM)
71
Data Watchpoint and Trace (DWT)
71
Flash Patch and Breakpoint (FPB)
71
Reserved
-
Cortex-M3 Peripherals (SysTick, NVIC, MPU and SCB)
119
Reserved
-
Trace Port Interface Unit (TPIU)
72
Reserved
-
2.4.1
2.4.2
Memory Regions, Types and Attributes
The memory map and the programming of the MPU split the memory map into regions. Each region
has a defined memory type, and some regions have additional memory attributes. The memory
type and attributes determine the behavior of accesses to the region.
The memory types are:
■ Normal: The processor can re-order transactions for efficiency and perform speculative reads.
■ Device: The processor preserves transaction order relative to other transactions to Device or
Strongly Ordered memory.
■ Strongly Ordered: The processor preserves transaction order relative to all other transactions.
The different ordering requirements for Device and Strongly Ordered memory mean that the memory
system can buffer a write to Device memory but must not buffer a write to Strongly Ordered memory.
An additional memory attribute is Execute Never (XN), which means the processor prevents
instruction accesses. A fault exception is generated only on execution of an instruction executed
from an XN region.
Memory System Ordering of Memory Accesses
For most memory accesses caused by explicit memory access instructions, the memory system
does not guarantee that the order in which the accesses complete matches the program order of
the instructions, providing the order does not affect the behavior of the instruction sequence. Normally,
if correct program execution depends on two memory accesses completing in program order,
software must insert a memory barrier instruction between the memory access instructions (see
“Software Ordering of Memory Accesses” on page 91).
However, the memory system does guarantee ordering of accesses to Device and Strongly Ordered
memory. For two memory access instructions A1 and A2, if both A1 and A2 are accesses to either
Device or Strongly Ordered memory, and if A1 occurs before A2 in program order, A1 is always
observed before A2.
90
October 06, 2012
Texas Instruments-Production Data