LM3S5956-IQR80-C1 Datasheet, PDF (648/1144 Pages) Texas Instruments – Stellaris® LM3S5956 Microcontroller

NRND: Not recommended for new designs.
Universal Asynchronous Receivers/Transmitters (UARTs)
Bit/Field
12:11
10
9
8
7
6
Name
reserved
OEMIS
BEMIS
PEMIS
FEMIS
RTMIS
Type
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Overrun Error Masked Interrupt Status
Value Description
1 An unmasked interrupt was signaled due to an overrun error.
0 An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the OEIC bit in the UARTICR register.
UART Break Error Masked Interrupt Status
Value Description
1 An unmasked interrupt was signaled due to a break error.
0 An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the BEIC bit in the UARTICR register.
UART Parity Error Masked Interrupt Status
Value Description
1 An unmasked interrupt was signaled due to a parity error.
0 An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the PEIC bit in the UARTICR register.
UART Framing Error Masked Interrupt Status
Value Description
1 An unmasked interrupt was signaled due to a framing error.
0 An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the FEIC bit in the UARTICR register.
UART Receive Time-Out Masked Interrupt Status
Value Description
1 An unmasked interrupt was signaled due to a receive time out.
0 An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the RTIC bit in the UARTICR register.
648
October 06, 2012
Texas Instruments-Production Data