LM3S5956-IQR80-C1 Datasheet, PDF (1043/1144 Pages) Texas Instruments – Stellaris® LM3S5956 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S5956 Microcontroller
22.1 Signals by Pin Number
Table 22-2. Signals by Pin Number
Pin Number
1
2
Pin Name
PE3
AIN0
CCP1
CCP7
PhB0
SSI1Tx
PE2
AIN1
CCP2
CCP4
PhA0
SSI1Rx
VDDA
Pin Type
I/O
I
I/O
I/O
I
O
I/O
I
I/O
I/O
I
I
-
3
GNDA
-
4
PE1
I/O
AIN2
I
CCP2
I/O
5
CCP6
I/O
Fault0
I
PWM5
O
SSI1Fss
I/O
PE0
I/O
AIN3
I
CCP3
I/O
6
PWM4
O
SSI1Clk
I/O
USB0PFLT
I
LDO
-
7
Buffer Type^a Description
TTL
GPIO port E bit 3.
Analog Analog-to-digital converter input 0.
TTL
Capture/Compare/PWM 1.
TTL
Capture/Compare/PWM 7.
TTL
QEI module 0 phase B.
TTL
SSI module 1 transmit.
TTL
GPIO port E bit 2.
Analog Analog-to-digital converter input 1.
TTL
Capture/Compare/PWM 2.
TTL
Capture/Compare/PWM 4.
TTL
QEI module 0 phase A.
TTL
SSI module 1 receive.
Power
The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be supplied with a voltage that meets
the specification in Table 24-2 on page 1068 , regardless of system
implementation.
Power
The ground reference for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from GND to minimize
the electrical noise contained on VDD from affecting the analog
functions.
TTL
GPIO port E bit 1.
Analog Analog-to-digital converter input 2.
TTL
Capture/Compare/PWM 2.
TTL
Capture/Compare/PWM 6.
TTL
PWM Fault 0.
TTL
PWM 5. This signal is controlled by PWM Generator 2.
TTL
SSI module 1 frame signal.
TTL
GPIO port E bit 0.
Analog Analog-to-digital converter input 3.
TTL
Capture/Compare/PWM 3.
TTL
PWM 4. This signal is controlled by PWM Generator 2.
TTL
SSI module 1 clock.
TTL
Optionally used in Host mode by an external power source to
indicate an error state by that power source.
Power
Low drop-out regulator output voltage. This pin requires an external
capacitor between the pin and GND of 1 µF or greater. The LDO
pin must also be connected to the VDDC pins at the board level in
addition to the decoupling capacitor(s).
October 06, 2012
Texas Instruments-Production Data
1043