LM3S5956-IQR80-C1 Datasheet, PDF (276/1144 Pages) Texas Instruments – Stellaris® LM3S5956 Microcontroller

System Control
NRND: Not recommended for new designs.
Bit/Field
4
3
2
1
0
Name
SSI0
reserved
UART2
UART1
UART0
Type
R/W
RO
R/W
R/W
R/W
Reset
0
0
0
0
0
Description
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART2 Clock Gating Control
This bit controls the clock gating for UART module 2. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
UART1 Clock Gating Control
This bit controls the clock gating for UART module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
276
October 06, 2012
Texas Instruments-Production Data