LM3S5956-IQR80-C1 Datasheet, PDF (300/1144 Pages) Texas Instruments – Stellaris® LM3S5956 Microcontroller

Hibernation Module
NRND: Not recommended for new designs.
Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000
This register is the current 32-bit value of the RTC counter.
Note:
HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and have special timing requirements. Software should
make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has
elapsed. If the WRC bit is clear, any attempted write access is ignored. See “Register Access
Timing” on page 292.
Hibernation RTC Counter (HIBRTCC)
Base 0x400F.C000
Offset 0x000
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RTCC
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RTCC
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:0
Name
RTCC
Type
Reset Description
RO 0x0000.0000 RTC Counter
A read returns the 32-bit counter value, which represents the seconds
elapsed since the RTC was enabled. This register is read-only. To
change the value, use the HIBRTCLD register.
300
October 06, 2012
Texas Instruments-Production Data