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LM3S5956-IQR80-C1 Datasheet, PDF (711/1144 Pages) Texas Instruments – Stellaris® LM3S5956 Microcontroller
NRND: Not recommended for new designs.
Stellaris® LM3S5956 Microcontroller
15.1 Block Diagram
Figure 15-1. I2C Block Diagram
Interrupt
I2C Control
I2CMSA
I2CMCS
I2CMDR
I2CMTPR
I2CMIMR
I2CMRIS
I2CMMIS
I2CMICR
I2CMCR
I2CSOAR
I2CSCSR
I2CSDR
I2CSIMR
I2CSRIS
I2CSMIS
I2CSICR
I2C Master Core
I2CSCL
I2CSDA
I2C Slave Core
I2CSCL
I2CSDA
I2C I/O Select
I2CSCL
I2CSDA
15.2
Signal Description
The following table lists the external signals of the I2C interface and describes the function of each.
The I2C interface signals are alternate functions for some GPIO signals and default to be GPIO
signals at reset., with the exception of the I2C0SCL and I2CSDA pins which default to the I2C
function. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin
placements for the I2C signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL)
register (page 431) should be set to choose the I2C function. The number in parentheses is the
encoding that must be programmed into the PMCn field in the GPIO Port Control (GPIOPCTL)
register (page 448) to assign the I2C signal to the specified GPIO port pin. Note that the I2C pins
should be set to open drain using the GPIO Open Drain Select (GPIOODR) register. For more
information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 411.
Table 15-1. I2C Signals (64LQFP)
Pin Name
I2C0SCL
I2C0SDA
I2C1SCL
I2C1SDA
Pin Number Pin Mux / Pin
Assignment
47
PB2 (1)
27
PB3 (1)
17
PA0 (8)
25
PA6 (1)
18
PA1 (8)
26
PA7 (1)
Pin Type
I/O
I/O
I/O
I/O
Buffer Typea Description
OD
I2C module 0 clock.
OD
I2C module 0 data.
OD
I2C module 1 clock.
OD
I2C module 1 data.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
15.3
Functional Description
Each I2C module is comprised of both master and slave functions. For proper operation, the SDA
and SCL pins must be configured as open-drain signals. A typical I2C bus configuration is shown
in Figure 15-2.
See “Inter-Integrated Circuit (I2C) Interface” on page 1082 for I2C timing diagrams.
October 06, 2012
711
Texas Instruments-Production Data