LM3S5956-IQR80-C1 Datasheet, PDF (650/1144 Pages) Texas Instruments – Stellaris® LM3S5956 Microcontroller

NRND: Not recommended for new designs.
Universal Asynchronous Receivers/Transmitters (UARTs)
Register 13: UART Interrupt Clear (UARTICR), offset 0x044
The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt
(both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.
UART Interrupt Clear (UARTICR)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
UART2 base: 0x4000.E000
Offset 0x044
Type W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LME5IC LME1IC LMSBIC
reserved
OEIC
BEIC
PEIC
FEIC
RTIC
TXIC
RXIC
reserved
Type W1C
W1C
W1C
RO
RO
W1C
W1C
W1C
W1C
W1C
W1C
W1C
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:16
15
14
13
12:11
10
9
8
7
Name
reserved
LME5IC
LME1IC
LMSBIC
reserved
OEIC
BEIC
PEIC
FEIC
Type
RO
W1C
W1C
W1C
RO
W1C
W1C
W1C
W1C
Reset
0
0
0
0
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
LIN Mode Edge 5 Interrupt Clear
Writing a 1 to this bit clears the LME5RIS bit in the UARTRIS register
and the LME5MIS bit in the UARTMIS register.
LIN Mode Edge 1 Interrupt Clear
Writing a 1 to this bit clears the LME1RIS bit in the UARTRIS register
and the LME1MIS bit in the UARTMIS register.
LIN Mode Sync Break Interrupt Clear
Writing a 1 to this bit clears the LMSBRIS bit in the UARTRIS register
and the LMSBMIS bit in the UARTMIS register.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Overrun Error Interrupt Clear
Writing a 1 to this bit clears the OERIS bit in the UARTRIS register and
the OEMIS bit in the UARTMIS register.
Break Error Interrupt Clear
Writing a 1 to this bit clears the BERIS bit in the UARTRIS register and
the BEMIS bit in the UARTMIS register.
Parity Error Interrupt Clear
Writing a 1 to this bit clears the PERIS bit in the UARTRIS register and
the PEMIS bit in the UARTMIS register.
Framing Error Interrupt Clear
Writing a 1 to this bit clears the FERIS bit in the UARTRIS register and
the FEMIS bit in the UARTMIS register.
650
October 06, 2012
Texas Instruments-Production Data