LM3S5956-IQR80-C1 Datasheet, PDF (7/1144 Pages) Texas Instruments – Stellaris® LM3S5956 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S5956 Microcontroller
12.3.3 Hardware Sample Averaging Circuit ............................................................................. 540
12.3.4 Analog-to-Digital Converter .......................................................................................... 540
12.3.5 Differential Sampling ................................................................................................... 543
12.3.6 Internal Temperature Sensor ........................................................................................ 546
12.3.7 Digital Comparator Unit ............................................................................................... 546
12.4 Initialization and Configuration ..................................................................................... 551
12.4.1 Module Initialization ..................................................................................................... 551
12.4.2 Sample Sequencer Configuration ................................................................................. 552
12.5 Register Map .............................................................................................................. 552
12.6 Register Descriptions .................................................................................................. 554
13 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 612
13.1 Block Diagram ............................................................................................................ 613
13.2 Signal Description ....................................................................................................... 613
13.3 Functional Description ................................................................................................. 614
13.3.1 Transmit/Receive Logic ............................................................................................... 614
13.3.2 Baud-Rate Generation ................................................................................................. 615
13.3.3 Data Transmission ...................................................................................................... 615
13.3.4 Serial IR (SIR) ............................................................................................................. 616
13.3.5 ISO 7816 Support ....................................................................................................... 617
13.3.6 LIN Support ................................................................................................................ 617
13.3.7 FIFO Operation ........................................................................................................... 619
13.3.8 Interrupts .................................................................................................................... 619
13.3.9 Loopback Operation .................................................................................................... 620
13.3.10 DMA Operation ........................................................................................................... 620
13.4 Initialization and Configuration ..................................................................................... 621
13.5 Register Map .............................................................................................................. 622
13.6 Register Descriptions .................................................................................................. 623
14 Synchronous Serial Interface (SSI) .................................................................... 668
14.1 Block Diagram ............................................................................................................ 669
14.2 Signal Description ....................................................................................................... 669
14.3 Functional Description ................................................................................................. 670
14.3.1 Bit Rate Generation ..................................................................................................... 670
14.3.2 FIFO Operation ........................................................................................................... 670
14.3.3 Interrupts .................................................................................................................... 671
14.3.4 Frame Formats ........................................................................................................... 672
14.3.5 DMA Operation ........................................................................................................... 679
14.4 Initialization and Configuration ..................................................................................... 680
14.5 Register Map .............................................................................................................. 681
14.6 Register Descriptions .................................................................................................. 682
15 Inter-Integrated Circuit (I²C) Interface ................................................................ 710
15.1 Block Diagram ............................................................................................................ 711
15.2 Signal Description ....................................................................................................... 711
15.3 Functional Description ................................................................................................. 711
15.3.1 I²C Bus Functional Overview ........................................................................................ 712
15.3.2 Available Speed Modes ............................................................................................... 714
15.3.3 Interrupts .................................................................................................................... 715
15.3.4 Loopback Operation .................................................................................................... 716
15.3.5 Command Sequence Flow Charts ................................................................................ 716
October 06, 2012
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