LM3S5956-IQR80-C1 Datasheet, PDF (1096/1144 Pages) Texas Instruments – Stellaris® LM3S5956 Microcontroller

Register Quick Reference
NRND: Not recommended for new designs.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FMPRE3, type R/W, offset 0x20C, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
FMPPE1, type R/W, offset 0x404, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
FMPPE2, type R/W, offset 0x408, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
FMPPE3, type R/W, offset 0x40C, reset 0xFFFF.FFFF
PROG_ENABLE
PROG_ENABLE
Micro Direct Memory Access (μDMA)
μDMA Channel Control Structure (Offset from Channel Control Table Base)
Base n/a
DMASRCENDP, type R/W, offset 0x000, reset -
ADDR
ADDR
DMADSTENDP, type R/W, offset 0x004, reset -
ADDR
ADDR
DMACHCTL, type R/W, offset 0x008, reset -
DSTINC
DSTSIZE
SRCINC
SRCSIZE
ARBSIZE
ARBSIZE
XFERSIZE
XFERMODE
Micro Direct Memory Access (μDMA)
μDMA Registers (Offset from μDMA Base Address)
Base 0x400F.F000
DMASTAT, type RO, offset 0x000, reset 0x001F.0000
DMACFG, type WO, offset 0x004, reset -
DMACTLBASE, type R/W, offset 0x008, reset 0x0000.0000
ADDR
DMAALTBASE, type RO, offset 0x00C, reset 0x0000.0200
DMAWAITSTAT, type RO, offset 0x010, reset 0xFFFF.FFC0
DMASWREQ, type WO, offset 0x014, reset -
DMAUSEBURSTSET, type R/W, offset 0x018, reset 0x0000.0000
ADDR
ADDR
ADDR
WAITREQ[n]
WAITREQ[n]
SWREQ[n]
SWREQ[n]
SET[n]
SET[n]
STATE
DMACHANS
MASTEN
MASTEN
1096
Texas Instruments-Production Data
October 06, 2012