LM3S5956-IQR80-C1 Datasheet, PDF (34/1144 Pages) Texas Instruments – Stellaris® LM3S5956 Microcontroller

Table of Contents
NRND: Not recommended for new designs.
Register 326: USB VBUS Droop Control Raw Interrupt Status (USBVDCRIS), offset 0x434 .................... 927
Register 327: USB VBUS Droop Control Interrupt Mask (USBVDCIM), offset 0x438 ............................... 928
Register 328: USB VBUS Droop Control Interrupt Status and Clear (USBVDCISC), offset 0x43C ............ 929
Register 329: USB ID Valid Detect Raw Interrupt Status (USBIDVRIS), offset 0x444 .............................. 930
Register 330: USB ID Valid Detect Interrupt Mask (USBIDVIM), offset 0x448 ......................................... 931
Register 331: USB ID Valid Detect Interrupt Status and Clear (USBIDVISC), offset 0x44C ...................... 932
Register 332: USB DMA Select (USBDMASEL), offset 0x450 ................................................................ 933
Analog Comparators ................................................................................................................... 935
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 .................................. 940
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ....................................... 941
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ......................................... 942
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ....................... 943
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020 ..................................................... 944
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040 ..................................................... 944
Register 7: Analog Comparator Control 0 (ACCTL0), offset 0x024 ..................................................... 945
Register 8: Analog Comparator Control 1 (ACCTL1), offset 0x044 ..................................................... 945
Pulse Width Modulator (PWM) .................................................................................................... 947
Register 1: PWM Master Control (PWMCTL), offset 0x000 ................................................................ 960
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 962
Register 3: PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 963
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 965
Register 5: PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 967
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 969
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 971
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 973
Register 9: PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 975
Register 10: PWM Fault Condition Value (PWMFAULTVAL), offset 0x024 ............................................ 977
Register 11: PWM Enable Update (PWMENUPD), offset 0x028 ........................................................... 979
Register 12: PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 982
Register 13: PWM1 Control (PWM1CTL), offset 0x080 ....................................................................... 982
Register 14: PWM2 Control (PWM2CTL), offset 0x0C0 ....................................................................... 982
Register 15: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 ..................................... 987
Register 16: PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 ..................................... 987
Register 17: PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4 .................................... 987
Register 18: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 ..................................................... 990
Register 19: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 ..................................................... 990
Register 20: PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 .................................................... 990
Register 21: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ............................................ 992
Register 22: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C ............................................ 992
Register 23: PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC ............................................ 992
Register 24: PWM0 Load (PWM0LOAD), offset 0x050 ........................................................................ 994
Register 25: PWM1 Load (PWM1LOAD), offset 0x090 ........................................................................ 994
Register 26: PWM2 Load (PWM2LOAD), offset 0x0D0 ....................................................................... 994
Register 27: PWM0 Counter (PWM0COUNT), offset 0x054 ................................................................. 995
Register 28: PWM1 Counter (PWM1COUNT), offset 0x094 ................................................................. 995
Register 29: PWM2 Counter (PWM2COUNT), offset 0x0D4 ................................................................ 995
Register 30: PWM0 Compare A (PWM0CMPA), offset 0x058 .............................................................. 996
Register 31: PWM1 Compare A (PWM1CMPA), offset 0x098 .............................................................. 996
34
October 06, 2012
Texas Instruments-Production Data