LM3S5956-IQR80-C1 Datasheet, PDF(1045/1144 Page) Texas Instruments – Stellaris® LM3S5956 Microcontroller

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

LM3S5956-IQR80-C1 Datasheet, PDF (1045/1144 Pages) Texas Instruments – Stellaris® LM3S5956 Microcontroller

◁

NRND: Not recommended for new designs.

StellarisÂ® LM3S5956 Microcontroller

Table 22-2. Signals by Pin Number (continued)

Pin Number

Pin Name

Pin Type Buffer Typea Description

PC7

I/O

TTL

GPIO port C bit 7.

C1+

I

Analog Analog comparator 1 positive input.

C1o

O

TTL

Analog comparator 1 output.

CCP0

I/O

TTL

Capture/Compare/PWM 0.

16

CCP4

I/O

TTL

Capture/Compare/PWM 4.

PhB0

I

TTL

QEI module 0 phase B.

U1Tx

O

TTL

UART module 1 transmit. When in IrDA mode, this signal has IrDA

modulation.

USB0PFLT

I

TTL

Optionally used in Host mode by an external power source to

indicate an error state by that power source.

PA0

I2C1SCL

I/O

TTL

GPIO port A bit 0.

I/O

OD

I2C module 1 clock.

17

U0Rx

I

TTL

UART module 0 receive. When in IrDA mode, this signal has IrDA

modulation.

U1Rx

I

TTL

UART module 1 receive. When in IrDA mode, this signal has IrDA

modulation.

PA1

I2C1SDA

I/O

TTL

GPIO port A bit 1.

I/O

OD

I2C module 1 data.

18

U0Tx

O

TTL

UART module 0 transmit. When in IrDA mode, this signal has IrDA

modulation.

U1Tx

O

TTL

UART module 1 transmit. When in IrDA mode, this signal has IrDA

modulation.

PA2

I/O

TTL

GPIO port A bit 2.

19

PWM4

O

TTL

PWM 4. This signal is controlled by PWM Generator 2.

SSI0Clk

I/O

TTL

SSI module 0 clock

PA3

I/O

TTL

GPIO port A bit 3.

20

PWM5

O

TTL

PWM 5. This signal is controlled by PWM Generator 2.

SSI0Fss

I/O

TTL

SSI module 0 frame signal

PA4

I/O

TTL

GPIO port A bit 4.

21

CAN0Rx

I

TTL

CAN module 0 receive.

SSI0Rx

I

TTL

SSI module 0 receive

PA5

I/O

TTL

GPIO port A bit 5.

22

CAN0Tx

O

TTL

CAN module 0 transmit.

SSI0Tx

O

TTL

SSI module 0 transmit

VDDC

23

-

Power Positive supply for most of the logic function, including the

processor core and most peripherals. The voltage on this pin is

1.3 V and is supplied by the on-chip LDO. The VDDC pins should

only be connected to the LDO pin and an external capacitor as

specified in .

24

GND

-

Power Ground reference for logic and I/O pins.

October 06, 2012

Texas Instruments-Production Data

1045

▷