LM3S5956-IQR80-C1 Datasheet, PDF (1006/1144 Pages) Texas Instruments – Stellaris® LM3S5956 Microcontroller

NRND: Not recommended for new designs.
Pulse Width Modulator (PWM)
Register 48: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset
0x070
Register 49: PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset
0x0B0
Register 50: PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset
0x0F0
The PWMnDBFALL register contains the number of clock cycles to delay the rising edge of the
pwmB' signal from the falling edge of the pwmA signal. If the dead-band generator is disabled
through the PWMnDBCTL register, this register is ignored. If the value of this register is larger than
the width of a Low pulse on the pwmA signal, the falling-edge delay consumes the entire Low time
of the signal, resulting in no Low time on the output. Care must be taken to ensure that the pwmA
Low time always exceeds the falling-edge delay.
If the Dead-Band Falling-Edge-Delay mode is immediate (based on the DBFALLUP field encoding
in the PWMnCTL register), the 12-bit FALLDELAY value is used immediately. If the update mode
is locally synchronized, this value is used the next time the counter reaches zero. If the update mode
is globally synchronized, this value is used the next time the counter reaches zero after a synchronous
update has been requested through the PWM Master Control (PWMCTL) register (see page 960).
If this register is rewritten before the actual update occurs, the previous value is never used and is
lost.
PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL)
PWM0 base: 0x4002.8000
Offset 0x070
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
Type RO
Reset
0
14
13
reserved
RO
RO
0
0
12
11
10
9
8
7
6
5
4
3
2
1
0
FALLDELAY
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:12
11:0
Name
reserved
FALLDELAY
Type
RO
R/W
Reset Description
0x0000.0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x000
Dead-Band Fall Delay
The number of clock cycles to delay the falling edge of pwmB' from the
rising edge of pwmA.
1006
Texas Instruments-Production Data
October 06, 2012