SM320LF2407-EP Datasheet, PDF (99/112 Pages) Texas Instruments – 
DSP CONTROLLERS

SM320LF2407AĆEP
DSP CONTROLLERS
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
peripheral register description (continued)
Table 18. LF240xA DSP Peripheral Register Description (Continued)
ADDR
BIT 15
BIT 7
07096h
07098h
07099h
0709Ah
0709Bh
0709Ch
0709Dh
0709Eh
0709Fh
—
—
A7DIR
IOPA7
B7DIR
IOPB7
C7DIR
IOPC7
—
—
070A0h
—
CONV PRE-
SCALE (CPS)
070A1h
EVB SOC
EN SEQ1
EXT SOC
EN SEQ1
—
070A2h
—
070A3h
070A4h
070A5h
070A6h
070A7h
070A8h
070A9h
070AAh
CONV 3
CONV 1
CONV 7
CONV 5
CONV 11
CONV 9
CONV 15
CONV 13
—
SEQ2
STATE 3
D9
D1
D9
D1
D9
D1
BIT 14
BIT 6
F6DIR
IOPF6
A6DIR
IOPA6
B6DIR
IOPB6
C6DIR
IOPC6
—
—
ADC
S/W RESET
CONTIN-
UOUS RUN
RESET
SEQ1
Reset SEQ2
—
MAXCONV2
2
CONV 3
CONV 1
CONV 7
CONV 5
CONV 11
CONV 9
CONV 15
CONV 13
—
SEQ2
STATE 2
D8
D0
D8
D0
D8
D0
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
DIGITAL I/O CONTROL REGISTERS (CONTINUED)
F5DIR
F4DIR
F3DIR
F2DIR
F1DIR
IOPF5
IOPF4
IOPF3
IOPF2
IOPF1
A5DIR
A4DIR
A3DIR
A2DIR
A1DIR
IOPA5
IOPA4
IOPA3
IOPA2
IOPA1
Illegal
B5DIR
B4DIR
B3DIR
B2DIR
B1DIR
IOPB5
IOPB4
IOPB3
IOPB2
IOPB1
Illegal
C5DIR
C4DIR
C3DIR
C2DIR
C1DIR
IOPC5
IOPC4
IOPC3
IOPC2
IOPC1
Illegal
—
—
—
—
—
—
—
—
—
—
Illegal
ANALOG-TO-DIGITAL CONVERTER (ADC) REGISTERS
SOFT
FREE
ACQ
ACQ
ACQ
PRESCALE3 PRESCALE2 PRESCALE1
INT
SEQ1/2
PRIORITY CASCADE
—
—
—
INT ENA
INT ENA
SOC SEQ1 SEQ1 BUSY _{SEQ1 Mode1 SEQ1 Mode0}
INT FLAG
SEQ1
SOC SEQ2
SEQ2 BUSY
INT ENA
SEQ2 Mode1
INT ENA
SEQ2 Mode0
INT FLAG
SEQ2
—
—
—
—
—
MAXCONV2 MAXCONV2 MAXCONV1 MAXCONV1 MAXCONV1
1
0
3
2
1
CONV 3
CONV 3
CONV 2
CONV 2
CONV 2
CONV 1
CONV 1
CONV 0
CONV 0
CONV 0
CONV 7
CONV 7
CONV 6
CONV 6
CONV 6
CONV 5
CONV 5
CONV 4
CONV 4
CONV 4
CONV 11
CONV 11
CONV 10
CONV 10
CONV 10
CONV 9
CONV 9
CONV 8
CONV 8
CONV 8
CONV 15
CONV 15
CONV 14
CONV 14
CONV 14
CONV 13
CONV 13
CONV 12
CONV 12
CONV 12
—
—
SEQ CNTR3 SEQ CNTR2 SEQ CNTR1
SEQ2
STATE 1
SEQ2
STATE 0
SEQ1
STATE 3
SEQ1
STATE 2
SEQ1
STATE 1
D7
D6
D5
D4
D3
0
0
0
0
0
D7
D6
D5
D4
D3
0
0
0
0
0
D7
D6
D5
D4
D3
0
0
0
0
0
BIT 8
BIT 0
F0DIR
IOPF0
A0DIR
IOPA0
B0DIR
IOPB0
C0DIR
IOPC0
D0DIR
IOPD0
ACQ
PRESCALE0
—
EVA SOC
EN SEQ1
EVB SOC
EN SEQ2
—
MAXCONV1
0
CONV 2
CONV 0
CONV 6
CONV 4
CONV 10
CONV 8
CONV 14
CONV 12
SEQ CNTR0
SEQ1
STATE 0
D2
0
D2
0
D2
0
REG
PFDATDIR
PADATDIR
PBDATDIR
PCDATDIR
PDDATDIR
ADCTRL1
ADCTRL2
MAXCONV
CHSELSEQ1
CHSELSEQ2
CHSELSEQ3
CHSELSEQ4
AUTO_SEQ_SR
RESULT0
RESULT1
RESULT2
Indicates change with respect to the F243/F241, C242 device register maps.
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