SM320LF2407-EP Datasheet, PDF (59/112 Pages) Texas Instruments – 
DSP CONTROLLERS

SM320LF2407AĆEP
DSP CONTROLLERS
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
recommended operating conditions^‡§
MIN
NOM
MAX
VDD/VDDO
VSS
PLLVCCA
VCCA¶
VCCP
fCLKOUT
Supply voltage
Supply ground
PLL supply voltage
ADC supply voltage
Flash programming supply voltage
Device clock frequency (system clock)
VIH#
High-level input voltage
VDDO = VDD ± 0.3 V
XTAL1/CLKIN
RS
All other inputs
D[15:0]
3
3.3
3.6
0
0
0
3
3.3
3.6
3
3.3
3.6
4.75
5
5.25
2
40
2.2
VDD + 0.3
2.3
VDD + 0.3
2
VDD + 0.3
0.6
VIL
Low-level input voltage
TCK
0.5
All other inputs
0.8
Output pins Group 1||
−2
IOH
High-level output source current, VOH = 2.4 V
Output pins Group 2||
−4
Output pins Group 3||
−8
Output pins Group 1||
2
IOL
Low-level output sink current, VOL = VOL MAX Output pins Group 2||
4
Output pins Group 3||
8
TC
Case temperature
M version
−55
125
TJ
Junction temperature
−40
25
130
Nf
Flash endurance for the array (Write/erase
cycles)
−40°C to 85°C
10K
‡ _{Refer to the mechanical data package page for thermal resistance values, ΘJA (junction-to-ambient) and ΘJC (junction-to-case).}
§ _{The drive strength of the EVA PWM pins and the EVB PWM pins are not identical.}
¶ _{VCCA should not differ from VDD by more than 0.3 V.}
# _{The input buffers used in 240x/240xA are not 5-V compatible.}
|| _{Primary signals and their groupings:}
Group 1: PWM1−PWM6, T1PWM, T2PWM, CAP1−CAP6, TCLKINA, IOPF6, IOPC1, TCK, TDI, TMS, XF, A0−A15
Group 2: PS/DS/IS, RD, W/R, STRB, R/W, VIS_OE, D0−D15, T3PWM, T4PWM, PWM7−PWM12, CANTX, CANRX, SPICLK,
SPISOMI, SPISIMO, SPISTE, EMU0, EMU1, TDO, TMS2
Group 3: TDIRA, TDIRB, SCIRXD, SCITXD, XINT1, XINT2, CLKOUT, TCLKINB
UNIT
V
V
V
V
V
MHz
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
°C
°C
cycles
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
59