SM320LF2407-EP Datasheet, PDF (78/112 Pages) Texas Instruments – 
DSP CONTROLLERS

SM320LF2407AĆEP
DSP CONTROLLERS
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
SPICLK
(clock polarity = 0)
SPICLK
(clock polarity = 1)
1
2
3
6
7
SPISIMO
Master Out Data Is Valid
SPISOMI
10
11
Master In Data
Must Be Valid
Data Valid
SPISTE†
† _{The SPISTE signal must be active before the SPI communication stream starts; the SPISTE signal must remain active until}
the SPI communication stream is complete.
Figure 35. SPI Master Mode External Timing (Clock Phase = 1)
78
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443