SM320LF2407-EP Datasheet, PDF (11/112 Pages) Texas Instruments – 
DSP CONTROLLERS

SM320LF2407AĆEP
DSP CONTROLLERS
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
pin functions (continued)
Table 2. LF240xA and LC240xA Pin List and Package Options^†‡ (Continued)
PIN NAME
LF2407A
(144-PGE)
DESCRIPTION
ADDRESS, DATA, AND MEMORY CONTROL SIGNALS (CONTINUED)
PS
84
Program space strobe. IS, DS, and PS are always high unless low-level asserted for access to the
relevant external memory space or I/O. They are placed in the high-impedance state.¶
Read/write qualifier signal. R/W indicates transfer direction during communication to an external
R/W
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device. It is normally in read mode (high), unless low level is asserted for performing a write operation.
R/W is placed in the high-impedance state.¶
W/R /
IOPC0
W/R
IOPC0
19
Write/Read qualifier or GPIO. This is an inverted R/W signal useful for zero-wait-state memory
interface. It is normally low, unless a memory write operation is performed. See Table 12, Port C
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section, for reset note regarding LF2406A and LF2402A. (↑)
RD
93
Read-enable strobe. Read-select indicates an active, external read cycle. RD is active on all external
program, data, and I / O reads. RD is placed in the high-impedance state.¶
Write-enable strobe. The falling edge of WE indicates that the device is driving the external data bus
WE
89
(D15 −D0). WE is active on all external program, data, and I/O writes. WE is placed in the
high-impedance state.¶
STRB
96
External memory access strobe. STRB is always high unless asserted low to indicate an external bus
cycle. STRB is active for all off-chip accesses. STRB is placed in the high-impedance state.¶
READY
READY is pulled low to add wait states for external accesses. READY indicates that an external device
is prepared for a bus transaction to be completed. If the device is not ready, it pulls the READY pin low.
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The processor waits one cycle and checks READY again. Note that the processor performs
READY-detection if at least one software wait state is programmed. To meet the external READY
timings, the wait-state generator control register (WSGR) should be programmed for at least one wait
state. (↑)
MP/MC
Microprocessor/Microcomputer mode select. If this pin is low during reset, the device is put in
microcomputer mode and program execution begins at 0000h of internal program memory (Flash
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EEPROM). A high value during reset puts the device in microprocessor mode and program execution
begins at 0000h of external program memory. This line sets the MP/MC bit (bit 2 in the SCSR2
register). (↓)
ENA_144
Active high to enable external interface signals. If pulled low, the 2407A behaves like the
122
2406A/2403A/2402A—i.e., it has no external memory and generates an illegal address if DS is
asserted. This pin has an internal pulldown. (↓)
VIS_OE
Visibility output enable (active when data bus is output). This pin is active (low) whenever the external
97
data bus is driving as an output during visibility mode. Can be used by external decode logic to prevent
data bus contention while running in visibility mode.
A0
80
Bit 0 of the 16-bit address bus
A1
78
Bit 1 of the 16-bit address bus
A2
74
Bit 2 of the 16-bit address bus
A3
71
Bit 3 of the 16-bit address bus
A4
68
Bit 4 of the 16-bit address bus
A5
64
Bit 5 of the 16-bit address bus
A6
61
Bit 6 of the 16-bit address bus
A7
57
Bit 7 of the 16-bit address bus
† _{Bold, italicized pin names indicate pin function after reset.}
‡ _{GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.}
§ _{It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy}
and improve the noise immunity of the ADC.
¶ _{Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high}
# _{No power supply pin (VDD, VDDO, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for proper}
device operation.
LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)
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